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<title>Static Call Graph - [.\Objects\GD32450ZKT6.axf]</title></head>
<body><HR>
<H1>Static Call Graph for image .\Objects\GD32450ZKT6.axf</H1><HR>
<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 5060960: Last Updated: Sat Jul 10 17:54:45 2021
<BR><P>
<H3>Maximum Stack Usage =        124 bytes + Unknown(Cycles, Untraceable Function Pointers)</H3><H3>
Call chain for Maximum Stack Depth:</H3>
main &rArr; usart_config &rArr; usart_baudrate_set &rArr; rcu_clock_freq_get
<P>
<H3>
Mutually Recursive functions
</H3> <LI><a href="#[1c]">ADC_IRQHandler</a>&nbsp;&nbsp;&nbsp;&rArr;&nbsp;&nbsp;&nbsp;<a href="#[1c]">ADC_IRQHandler</a><BR>
</UL>
<P>
<H3>
Function Pointers
</H3><UL>
 <LI><a href="#[1c]">ADC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4]">BusFault_Handler</a> from gd32f4xx_it.o(i.BusFault_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[20]">CAN0_EWMC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1e]">CAN0_RX0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1f]">CAN0_RX1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1d]">CAN0_TX_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[49]">CAN1_EWMC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[47]">CAN1_RX0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[48]">CAN1_RX1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[46]">CAN1_TX_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[55]">DCI_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[15]">DMA0_Channel0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[16]">DMA0_Channel1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[17]">DMA0_Channel2_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[18]">DMA0_Channel3_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[19]">DMA0_Channel4_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1a]">DMA0_Channel5_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1b]">DMA0_Channel6_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[39]">DMA0_Channel7_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[41]">DMA1_Channel0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[42]">DMA1_Channel1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[43]">DMA1_Channel2_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[44]">DMA1_Channel3_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[45]">DMA1_Channel4_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4b]">DMA1_Channel5_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4c]">DMA1_Channel6_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4d]">DMA1_Channel7_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[7]">DebugMon_Handler</a> from gd32f4xx_it.o(i.DebugMon_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[10]">EXTI0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[32]">EXTI10_15_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[11]">EXTI1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[12]">EXTI2_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[13]">EXTI3_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[14]">EXTI4_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[21]">EXTI5_9_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[e]">FMC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[57]">FPU_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2]">HardFault_Handler</a> from gd32f4xx_it.o(i.HardFault_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2a]">I2C0_ER_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[29]">I2C0_EV_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2c]">I2C1_ER_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2b]">I2C1_EV_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[50]">I2C2_ER_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4f]">I2C2_EV_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[b]">LVD_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3]">MemManage_Handler</a> from gd32f4xx_it.o(i.MemManage_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[1]">NMI_Handler</a> from gd32f4xx_it.o(i.NMI_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[8]">PendSV_Handler</a> from gd32f4xx_it.o(i.PendSV_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[f]">RCU_CTC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[33]">RTC_Alarm_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[d]">RTC_WKUP_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[0]">Reset_Handler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3a]">SDIO_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2d]">SPI0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2e]">SPI1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3c]">SPI2_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[6]">SVC_Handler</a> from gd32f4xx_it.o(i.SVC_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[9]">SysTick_Handler</a> from gd32f4xx_it.o(i.SysTick_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[59]">SystemInit</a> from system_gd32f4xx.o(i.SystemInit) referenced from startup_gd32f405.o(.text)
 <LI><a href="#[c]">TAMPER_STAMP_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[22]">TIMER0_BRK_TIMER8_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[25]">TIMER0_CC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[24]">TIMER0_TRG_CMT_TIMER10_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[23]">TIMER0_UP_TIMER9_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[26]">TIMER1_IRQHandler</a> from timer.o(i.TIMER1_IRQHandler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[27]">TIMER2_IRQHandler</a> from timer.o(i.TIMER2_IRQHandler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[28]">TIMER3_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3b]">TIMER4_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3f]">TIMER5_DAC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[40]">TIMER6_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[35]">TIMER7_BRK_TIMER11_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[38]">TIMER7_CC_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[37]">TIMER7_TRG_CMT_TIMER13_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[36]">TIMER7_UP_TIMER12_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[56]">TRNG_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3d]">UART3_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[3e]">UART4_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[2f]">USART0_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[30]">USART1_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[31]">USART2_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4e]">USART5_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[4a]">USBFS_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[34]">USBFS_WKUP_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[52]">USBHS_EP1_In_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[51]">USBHS_EP1_Out_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[54]">USBHS_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[53]">USBHS_WKUP_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[5]">UsageFault_Handler</a> from gd32f4xx_it.o(i.UsageFault_Handler) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[a]">WWDGT_IRQHandler</a> from startup_gd32f405.o(.text) referenced from startup_gd32f405.o(RESET)
 <LI><a href="#[5a]">__main</a> from entry.o(.ARM.Collect$$$$00000000) referenced from startup_gd32f405.o(.text)
 <LI><a href="#[58]">main</a> from main.o(i.main) referenced from entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P>
<H3>
Global Symbols
</H3>
<P><STRONG><a name="[5a]"></a>__main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry.o(.ARM.Collect$$$$00000000))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(.text)
</UL>
<P><STRONG><a name="[7e]"></a>_main_stk</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry2.o(.ARM.Collect$$$$00000001))

<P><STRONG><a name="[5b]"></a>_main_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Calls]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>

<P><STRONG><a name="[5d]"></a>__main_after_scatterload</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry5.o(.ARM.Collect$$$$00000004))
<BR><BR>[Called By]<UL><LI><a href="#[5c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload
</UL>

<P><STRONG><a name="[7f]"></a>_main_clock</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry7b.o(.ARM.Collect$$$$00000008))

<P><STRONG><a name="[80]"></a>_main_cpp_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry8b.o(.ARM.Collect$$$$0000000A))

<P><STRONG><a name="[81]"></a>_main_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry9a.o(.ARM.Collect$$$$0000000B))

<P><STRONG><a name="[82]"></a>__rt_lib_shutdown_fini</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry12b.o(.ARM.Collect$$$$0000000E))

<P><STRONG><a name="[83]"></a>__rt_final_cpp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry10a.o(.ARM.Collect$$$$0000000F))

<P><STRONG><a name="[84]"></a>__rt_final_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, entry11a.o(.ARM.Collect$$$$00000011))

<P><STRONG><a name="[62]"></a>enableAllInt</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, main.o(.emb_text))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[85]"></a>disableAllInt</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, main.o(.emb_text), UNUSED)

<P><STRONG><a name="[0]"></a>Reset_Handler</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1c]"></a>ADC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Called By]<UL><LI><a href="#[1c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;ADC_IRQHandler
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[20]"></a>CAN0_EWMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1e]"></a>CAN0_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1f]"></a>CAN0_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1d]"></a>CAN0_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[49]"></a>CAN1_EWMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[47]"></a>CAN1_RX0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[48]"></a>CAN1_RX1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[46]"></a>CAN1_TX_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[55]"></a>DCI_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[15]"></a>DMA0_Channel0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[16]"></a>DMA0_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[17]"></a>DMA0_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[18]"></a>DMA0_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[19]"></a>DMA0_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1a]"></a>DMA0_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1b]"></a>DMA0_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[39]"></a>DMA0_Channel7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[41]"></a>DMA1_Channel0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[42]"></a>DMA1_Channel1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[43]"></a>DMA1_Channel2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[44]"></a>DMA1_Channel3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[45]"></a>DMA1_Channel4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4b]"></a>DMA1_Channel5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4c]"></a>DMA1_Channel6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4d]"></a>DMA1_Channel7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[10]"></a>EXTI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[32]"></a>EXTI10_15_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[11]"></a>EXTI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[12]"></a>EXTI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[13]"></a>EXTI3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[14]"></a>EXTI4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[21]"></a>EXTI5_9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[e]"></a>FMC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[57]"></a>FPU_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2a]"></a>I2C0_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[29]"></a>I2C0_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2c]"></a>I2C1_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2b]"></a>I2C1_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[50]"></a>I2C2_ER_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4f]"></a>I2C2_EV_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[b]"></a>LVD_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[f]"></a>RCU_CTC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[33]"></a>RTC_Alarm_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[d]"></a>RTC_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3a]"></a>SDIO_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2d]"></a>SPI0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2e]"></a>SPI1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3c]"></a>SPI2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[c]"></a>TAMPER_STAMP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[22]"></a>TIMER0_BRK_TIMER8_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[25]"></a>TIMER0_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[24]"></a>TIMER0_TRG_CMT_TIMER10_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[23]"></a>TIMER0_UP_TIMER9_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[28]"></a>TIMER3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3b]"></a>TIMER4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3f]"></a>TIMER5_DAC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[40]"></a>TIMER6_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[35]"></a>TIMER7_BRK_TIMER11_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[38]"></a>TIMER7_CC_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[37]"></a>TIMER7_TRG_CMT_TIMER13_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[36]"></a>TIMER7_UP_TIMER12_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[56]"></a>TRNG_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3d]"></a>UART3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3e]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2f]"></a>USART0_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[30]"></a>USART1_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[31]"></a>USART2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4e]"></a>USART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[4a]"></a>USBFS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[34]"></a>USBFS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[52]"></a>USBHS_EP1_In_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[51]"></a>USBHS_EP1_Out_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[54]"></a>USBHS_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[53]"></a>USBHS_WKUP_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[a]"></a>WWDGT_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_gd32f405.o(.text))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[5c]"></a>__scatterload</STRONG> (Thumb, 28 bytes, Stack size 0 bytes, init.o(.text))
<BR><BR>[Calls]<UL><LI><a href="#[5d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main_after_scatterload
</UL>
<BR>[Called By]<UL><LI><a href="#[5b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_main_scatterload
</UL>

<P><STRONG><a name="[86]"></a>__scatterload_rt2</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, init.o(.text), UNUSED)

<P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.BusFault_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[7]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.DebugMon_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.HardFault_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[3]"></a>MemManage_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.MemManage_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.NMI_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[8]"></a>PendSV_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.PendSV_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[6]"></a>SVC_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.SVC_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[9]"></a>SysTick_Handler</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, gd32f4xx_it.o(i.SysTick_Handler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = SysTick_Handler
</UL>
<BR>[Calls]<UL><LI><a href="#[5e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;delay_decrement
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[59]"></a>SystemInit</STRONG> (Thumb, 104 bytes, Stack size 8 bytes, system_gd32f4xx.o(i.SystemInit))
<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = SystemInit &rArr; system_clock_config
</UL>
<BR>[Calls]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_config
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(.text)
</UL>
<P><STRONG><a name="[26]"></a>TIMER1_IRQHandler</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, timer.o(i.TIMER1_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIMER1_IRQHandler
</UL>
<BR>[Calls]<UL><LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_get
<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_clear
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[27]"></a>TIMER2_IRQHandler</STRONG> (Thumb, 32 bytes, Stack size 8 bytes, timer.o(i.TIMER2_IRQHandler))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = TIMER2_IRQHandler
</UL>
<BR>[Calls]<UL><LI><a href="#[60]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_get
<LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_clear
</UL>
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_it.o(i.UsageFault_Handler))
<BR>[Address Reference Count : 1]<UL><LI> startup_gd32f405.o(RESET)
</UL>
<P><STRONG><a name="[87]"></a>__scatterload_copy</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_copy), UNUSED)

<P><STRONG><a name="[88]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_null), UNUSED)

<P><STRONG><a name="[89]"></a>__scatterload_zeroinit</STRONG> (Thumb, 14 bytes, Stack size unknown bytes, handlers.o(i.__scatterload_zeroinit), UNUSED)

<P><STRONG><a name="[5e]"></a>delay_decrement</STRONG> (Thumb, 18 bytes, Stack size 0 bytes, systick.o(i.delay_decrement))
<BR><BR>[Called By]<UL><LI><a href="#[9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
</UL>

<P><STRONG><a name="[75]"></a>gpio_af_set</STRONG> (Thumb, 94 bytes, Stack size 20 bytes, gd32f4xx_gpio.o(i.gpio_af_set))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = gpio_af_set
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[6a]"></a>gpio_bit_reset</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_gpio.o(i.gpio_bit_reset))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[69]"></a>gpio_bit_set</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, gd32f4xx_gpio.o(i.gpio_bit_set))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[67]"></a>gpio_mode_set</STRONG> (Thumb, 78 bytes, Stack size 20 bytes, gd32f4xx_gpio.o(i.gpio_mode_set))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = gpio_mode_set
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[68]"></a>gpio_output_options_set</STRONG> (Thumb, 66 bytes, Stack size 20 bytes, gd32f4xx_gpio.o(i.gpio_output_options_set))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = gpio_output_options_set
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[58]"></a>main</STRONG> (Thumb, 120 bytes, Stack size 0 bytes, main.o(i.main))
<BR><BR>[Stack]<UL><LI>Max Depth = 124<LI>Call Chain = main &rArr; usart_config &rArr; usart_baudrate_set &rArr; rcu_clock_freq_get
</UL>
<BR>[Calls]<UL><LI><a href="#[6d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_data_transmit
<LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
<LI><a href="#[63]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_vector_table_set
<LI><a href="#[64]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_priority_group_set
<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_output_options_set
<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_mode_set
<LI><a href="#[69]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_set
<LI><a href="#[6a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_bit_reset
<LI><a href="#[62]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;enableAllInt
</UL>
<BR>[Address Reference Count : 1]<UL><LI> entry9a.o(.ARM.Collect$$$$0000000B)
</UL>
<P><STRONG><a name="[72]"></a>nvic_irq_enable</STRONG> (Thumb, 156 bytes, Stack size 20 bytes, gd32f4xx_misc.o(i.nvic_irq_enable))
<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = nvic_irq_enable
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
</UL>

<P><STRONG><a name="[64]"></a>nvic_priority_group_set</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, gd32f4xx_misc.o(i.nvic_priority_group_set))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[63]"></a>nvic_vector_table_set</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, gd32f4xx_misc.o(i.nvic_vector_table_set))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[74]"></a>rcu_clock_freq_get</STRONG> (Thumb, 264 bytes, Stack size 84 bytes, gd32f4xx_rcu.o(i.rcu_clock_freq_get))
<BR><BR>[Stack]<UL><LI>Max Depth = 84<LI>Call Chain = rcu_clock_freq_get
</UL>
<BR>[Called By]<UL><LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_baudrate_set
</UL>

<P><STRONG><a name="[66]"></a>rcu_periph_clock_enable</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, gd32f4xx_rcu.o(i.rcu_periph_clock_enable))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
<LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[7d]"></a>rcu_periph_reset_disable</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, gd32f4xx_rcu.o(i.rcu_periph_reset_disable))
<BR><BR>[Called By]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_deinit
</UL>

<P><STRONG><a name="[7c]"></a>rcu_periph_reset_enable</STRONG> (Thumb, 32 bytes, Stack size 0 bytes, gd32f4xx_rcu.o(i.rcu_periph_reset_enable))
<BR><BR>[Called By]<UL><LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_deinit
</UL>

<P><STRONG><a name="[6b]"></a>timer1_config</STRONG> (Thumb, 86 bytes, Stack size 24 bytes, timer.o(i.timer1_config))
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = timer1_config &rArr; nvic_irq_enable
</UL>
<BR>[Calls]<UL><LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_clear
<LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_enable
<LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_init
<LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_enable
<LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_irq_enable
<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
</UL>
<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[6c]"></a>timer2_config</STRONG> (Thumb, 82 bytes, Stack size 24 bytes, timer.o(i.timer2_config))
<BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = timer2_config &rArr; nvic_irq_enable
</UL>
<BR>[Calls]<UL><LI><a href="#[61]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_flag_clear
<LI><a href="#[70]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_interrupt_enable
<LI><a href="#[6f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_init
<LI><a href="#[71]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer_enable
<LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_irq_enable
<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
</UL>
<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[71]"></a>timer_enable</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, gd32f4xx_timer.o(i.timer_enable))
<BR><BR>[Called By]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
</UL>

<P><STRONG><a name="[6f]"></a>timer_init</STRONG> (Thumb, 122 bytes, Stack size 0 bytes, gd32f4xx_timer.o(i.timer_init))
<BR><BR>[Called By]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
</UL>

<P><STRONG><a name="[70]"></a>timer_interrupt_enable</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, gd32f4xx_timer.o(i.timer_interrupt_enable))
<BR><BR>[Called By]<UL><LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
</UL>

<P><STRONG><a name="[61]"></a>timer_interrupt_flag_clear</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, gd32f4xx_timer.o(i.timer_interrupt_flag_clear))
<BR><BR>[Called By]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER2_IRQHandler
<LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER1_IRQHandler
<LI><a href="#[6c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer2_config
<LI><a href="#[6b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;timer1_config
</UL>

<P><STRONG><a name="[60]"></a>timer_interrupt_flag_get</STRONG> (Thumb, 24 bytes, Stack size 0 bytes, gd32f4xx_timer.o(i.timer_interrupt_flag_get))
<BR><BR>[Called By]<UL><LI><a href="#[27]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER2_IRQHandler
<LI><a href="#[26]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIMER1_IRQHandler
</UL>

<P><STRONG><a name="[73]"></a>usart_baudrate_set</STRONG> (Thumb, 232 bytes, Stack size 32 bytes, gd32f4xx_usart.o(i.usart_baudrate_set))
<BR><BR>[Stack]<UL><LI>Max Depth = 116<LI>Call Chain = usart_baudrate_set &rArr; rcu_clock_freq_get
</UL>
<BR>[Calls]<UL><LI><a href="#[74]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_clock_freq_get
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[65]"></a>usart_config</STRONG> (Thumb, 152 bytes, Stack size 8 bytes, usartconf.o(i.usart_config))
<BR><BR>[Stack]<UL><LI>Max Depth = 124<LI>Call Chain = usart_config &rArr; usart_baudrate_set &rArr; rcu_clock_freq_get
</UL>
<BR>[Calls]<UL><LI><a href="#[78]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_word_length_set
<LI><a href="#[7a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_transmit_config
<LI><a href="#[79]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_stop_bit_set
<LI><a href="#[77]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_parity_config
<LI><a href="#[7b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_enable
<LI><a href="#[76]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_deinit
<LI><a href="#[73]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_baudrate_set
<LI><a href="#[75]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_af_set
<LI><a href="#[72]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;nvic_irq_enable
<LI><a href="#[66]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_clock_enable
<LI><a href="#[68]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_output_options_set
<LI><a href="#[67]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;gpio_mode_set
</UL>
<BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[6d]"></a>usart_data_transmit</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_data_transmit))
<BR><BR>[Called By]<UL><LI><a href="#[58]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
</UL>

<P><STRONG><a name="[76]"></a>usart_deinit</STRONG> (Thumb, 210 bytes, Stack size 8 bytes, gd32f4xx_usart.o(i.usart_deinit))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = usart_deinit
</UL>
<BR>[Calls]<UL><LI><a href="#[7c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_enable
<LI><a href="#[7d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;rcu_periph_reset_disable
</UL>
<BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[7b]"></a>usart_enable</STRONG> (Thumb, 10 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_enable))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[77]"></a>usart_parity_config</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_parity_config))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[79]"></a>usart_stop_bit_set</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_stop_bit_set))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[7a]"></a>usart_transmit_config</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_transmit_config))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>

<P><STRONG><a name="[78]"></a>usart_word_length_set</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, gd32f4xx_usart.o(i.usart_word_length_set))
<BR><BR>[Called By]<UL><LI><a href="#[65]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;usart_config
</UL>
<P>
<H3>
Local Symbols
</H3>
<P><STRONG><a name="[6e]"></a>system_clock_200m_25m_hxtal</STRONG> (Thumb, 238 bytes, Stack size 0 bytes, system_gd32f4xx.o(i.system_clock_200m_25m_hxtal))
<BR><BR>[Called By]<UL><LI><a href="#[5f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_config
</UL>

<P><STRONG><a name="[5f]"></a>system_clock_config</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, system_gd32f4xx.o(i.system_clock_config))
<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = system_clock_config
</UL>
<BR>[Calls]<UL><LI><a href="#[6e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;system_clock_200m_25m_hxtal
</UL>
<BR>[Called By]<UL><LI><a href="#[59]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemInit
</UL>
<P>
<H3>
Undefined Global Symbols
</H3><HR></body></html>
